ASIC DESIGN BY SMITH EBOOK

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Addressing the trend in industry away from fully-custom chip design to Michael Smith is both an experienced ASIC designer and a creative educator, with. Application Specific Integrated Circuits Addison Wesley Michael John Sebastian Smith. ASICs by M J Smith - Free ebook download as PDF File .pdf), Text File .txt) how to design an ASIC that may include large cells such as microprocessors, but.


Asic Design By Smith Ebook

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Michael John Sebastian Smith. This course is based on ASICs the book. Application-Specific Integrated Circuits. Michael J. S. Smith. VLSI Design Series. Application Specific Integrated Circuits Addison Wesley Michael John Sebastian Smith Pdf. Version, [version]. Download, Stock, [quota]. ASIC Design Class Notes This note covers the following topics: Introduction to ASIC Design, Timing, Verilog, FSMs, Hierarchy, Complexity, Tricks and.

Thanks in advance. For this we need to consider so much physical effects and package characteristics,so to learn this things,like this is there is any good books are there?

ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems

You just need a good book and some practice. There are many books for vhdl learning, you could google it. Enjoy study. Advanced asic chip Synthesis 2. Hi to everyone, I am new to this discussionboard. Benjamin-Cummings, p. Mead, C. Price, T. Shoji, M. See also Shoji, M. Addison-Wesley, , p. S56 Weste, N. A Systems Perspective. Concentrates on full-custom design. Wolf, W. A Systems Approach. Veendrick, H. A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals using open and closed for switches is confusingfor the same reason we say a tap is on and not that it is closed.

The transistor source and drain terminals are equivalent as far as digital signals are concernedwe do not worry about labeling an electrical switch with two terminals. Uppercase letters denote DC, large-signal, or steady-state voltages. The 'C' denotes that the supply is connected indirectly to the collectors of the npn bipolar transistors a bipolar transistor has a collector, base, and emitter corresponding roughly to the drain, gate, and source of an MOS transistor.

We turn a transistor on or off using the gate terminal. There are two kinds of CMOS transistors: A p -channel transistor requires a logic '0' again from now on, Ill just say a '0' on the gate to make the switch nonconducting to turn the transistor off.

The p -channel transistor symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn the transistor on. All this is shown in Figure 2. If we connect an n -channel transistor in series with a p -channel transistor, as shown in Figure 2. We can also make a two-input NOR gate Figure 2. Logic designers normally use the terms NAND gate and logic gate or just gate , but I shall try to use the terms NAND cell and logic cell rather than NAND gate or logic gate in this chapter to avoid any possible confusion with the gate terminal of a transistor.

The n -channel and p -channel transistor switches implement the '1's and '0's of a Karnaugh map. The region between source and drain is normally nonconducting. To make an n -channel transistor conducting, we must apply a positive voltage V GS the gate voltage with respect to the source that is greater than the n -channel transistor threshold voltage , V t n a typical value is 0.

To make current flow in an n -channel transistor we must also apply a positive voltage, V DS , to the drain with respect to the source. Figure 2. For an n -channel transistor we must connect the bulk to the most negative potential, GND or VSS, to reverse bias the bulk-to-drain and bulk-to-source pn -diodes. The arrow in the four-terminal n -channel transistor symbol in Figure 2.

The gate-oxide thickness, T OX , is approximately angstroms 0. The bulk may be either the substrate or a well. The diodes represent pn -junctions that must be reverse-biased. We need to find Q and t f. The velocity of the electrons v a vector is given by the equation that forms the basis of Ohms law: Equation 2. Next we find the channel charge, Q. The channel and the gate form the plates of a capacitor, separated by an insulatorthe gate oxide.

Our lower plate, the channel, is not a linear conductor. Charge only appears on the lower plate when the voltage between the gate and the channel, V GC , exceeds the n -channel threshold voltage. For our nonlinear capacitor we need to modify the equation for a linear capacitor to the following: The lower plate of our capacitor is resistive and conducting current, so that the potential in the channel, V GC , varies. The gate capacitance, C , is given by the formula for a parallel-plate capacitor with length L , width W , and plate separation equal to the gate-oxide thickness, T ox.

The constant k ' n is the process transconductance parameter or intrinsic transconductance: Clearly a small amount of charge remains or the current would go to zero, but with very little free charge the channel resistance in a small region close to the drain increases rapidly and any further increase in V DS is dropped over this region.

We can fit Eq. This value of k ' n , calculated in the saturation region, will be different typically lower by a factor of 2 or more from the value of k ' n measured in the linear region. We assumed the mobility, m n , and the threshold voltage, V t n , are constantsneither of which is true, as we shall see in Section 2. The next section explains the signs in Eq. A short-channel transistor shows a more linear characteristic due to velocity saturation. Normally, all of the transistors used on an ASIC have short channels.

The source of an n -channel transistor is lower in potential than the drain and vice versa for a p -channel transistor. In an n -channel transistor the threshold voltage, V t n , is normally positive, and the terminal voltages V DS and V GS are also usually positive.

In a p -channel transistor V t p is normally negative and we have a choice: We can write everything in terms of the magnitudes of the voltages and currents or we can use negative signs in a consistent fashion.

Here are the equations for a p -channel transistor using negative signs: The current I DSp is then negative, corresponding to conventional current flowing from source to drain of a p -channel transistor and hence the negative sign for I DSp sat in Eq. There are three reasons for this error. First, the threshold voltage is not constant. Second, the actual length of the channel the electrical or effective length, often written as L eff is less than the drawn mask length.

The third reason is that Eq. We can see this behavior for the short-channel transistor characteristics in Figure 2. Transistor current is often specified per micron of gate width because of the form of Eq. The value for v max n is lower than the 10 5 ms 1 we expected because the carrier velocity is also lowered by mobility degradation due the vertical electric field which we have ignored.

This vertical field forces the carriers to keep bumping in to the interface between the silicon and the gate oxide, slowing them down. Table 2. Many of the other parameters model velocity saturation and mobility degradation and thus the effective value of k ' n and k ' p. TABLE 2. The n-channel transistor characteristics are shown in Figure 2. The bulk connection for the n -channel transistor in Figure 2.

The bulk connection for the p -channel transistor is an n -well. The remaining connections show what happens when we try and pass a logic signal between the drain and source terminals.

V t n is positive and V t p is negative. The depth of the channels is greatly exaggerated. In Figure 2.

The application of these voltages makes the n -channel transistor conduct current, and electrons flow from source to drain. Suppose the drain is initially at logic '1'; then the n -channel transistor will begin to discharge any capacitance that is connected to its drain due to another logic cell, for example. The transistor will strongly object to attempts to change its drain terminal from a logic '0'. We say that the logic level at the drain is a strong '0'. The situation is now quite differentthe transistor is still on but V GS is decreasing as the source voltage approaches its final value.

In fact, the source terminal never gets to a logic '1'the source will stop increasing in voltage when V GS reaches V t n. At this point the transistor is very nearly off and the source voltage creeps slowly up to V DD V t n. Because the transistor is very nearly off, it would be easy for a logic cell connected to the source to change the potential there, since there is so little channel charge. The logic level at the source is a weak '1'.

In summary, we have the following logic levels: Sometimes we refer to the weak versions of '0' and '1' as degraded logic levels.

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In CMOS technology we can use both types of transistor together to produce strong '0' logic levels as well as strong '1' logic levels. The starting material is silicon, Si, refined from quartzite with less than 1 impurity in 10 10 silicon atoms. This method is known as Czochralski growth. Acceptor p -type or donor n -type dopants may be introduced into the melt to alter the type of silicon grown.

The boule is drawn so that the wafer surface is either in the or crystal planes. A smaller secondary flat indicates the wafer crystalline orientation and doping type. Wafers are made by chemical companies and sold to the IC manufacturers. To begin IC fabrication we place a batch of wafers a wafer lot on a boat and grow a layer typically a few thousand angstroms of silicon dioxide , SiO 2 , using a furnace.

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Silicon is used in the semiconductor industry not so much for the properties of silicon, but because of the physical, chemical, and electrical properties of its native oxide, SiO 2. An IC fabrication process contains a series of masking steps that in turn contain other steps to create the layers that define the transistors and metal interconnect.

Grow crystalline silicon 1 ; make a wafer 23 ; grow a silicon dioxide oxide layer in a furnace 4 ; apply liquid photoresist resist 5 ; mask exposure 6 ; a cross-section through a wafer showing the developed resist 7 ; etch the oxide layer 8 ; ion implantation ; strip the resist 11 ; strip the oxide Steps similar to are repeated for each layer typically times for a CMOS process.

Each masking step starts by spinning a thin layer approximately 1 m m of liquid photoresist resist onto each wafer. The UV light alters the structure of the resist, allowing it to be removed by developing. The exposed oxide may then be etched removed. Dry plasma etching etches in the vertical direction much faster than it does horizontally an anisotropic etch. Wet etch techniques are usually isotropic.

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The resist functions as a mask during the etch step and transfers the desired pattern to the oxide layer. Dopant ions are then introduced into the exposed silicon areas. An ion implanter is a cross between a TV and a mass spectrometer and fires dopant ions into the silicon wafer. Ions can only penetrate materials to a depth the range , normally a few microns that depends on the closely controlled implant energy measured in keVusually between 10 and keV; an electron volt, 1 eV, is 1.

By using layers of resist, oxide, and polysilicon we can prevent dopant ions from reaching the silicon surface and thus block the silicon from receiving an implant. We control the doping level by counting the number of ions we implant by integrating the ion-beam current. As an alternative to ion implantation we may instead strip the resist and introduce dopants by diffusion from a gaseous source in a furnace.

Once we have completed the transistor diffusion layers we can deposit layers of other materials. Metal layers can be deposited using sputtering. All these layers are patterned using masks and similar photolithography steps to those shown in Figure 2.

A process in which the effective gate length is less than 1 m m is referred to as a submicron process. Gate lengths below 0. This means that the drawn layers do not correspond directly to the masks in all cases. The active mask is the union of the ndiff and pdiff drawn layers. The n -diffusion implant and p -diffusion implant masks are bloated versions of the ndiff and pdiff drawn layers.

Often an ASIC vendor hides the details of the internal cell construction. The phantom cell is used for layout by the customer and then instantiated by the ASIC vendor after layout is complete. This layout uses grayscale stipple patterns to distinguish between layers.

We can construct wells in a CMOS process in several ways. In an n-well process , the substrate is p -type the wafer itself and we use an n -well mask to build the n -well.

We do not need a p -well mask because there are no p -wells in an n -well processthe n -channel transistors all sit in the substrate the wafer but we often draw the p -well layer as though it existed. In a p-well process we use a p -well mask to make the p -wells and the n -wells are the substrate.

There are even triple-well processes used to achieve even more control over the transistor performance. The bulk connections for CMOS transistors are not usually drawn in digital circuit schematics, but these substrate contacts well contacts or tub ties are very important. The active mask CAA leaves this nitride layer only in the active areas that will later become transistors or substrate contacts.

Everything outside the active areas is known as the field region, or just field. Next we implant the substrate to prevent unwanted transistors from forming in the field regionthis is the field implant or channel-stop implant. The nitride over the active areas acts as an implant mask and we may use another field-implant mask at this step also. The FOX will not grow over the nitride areas. When we strip the nitride we are left with FOX in the areas we do not want to dope the silicon.

Next we create the doped regions that form the sources, drains, and substrate contacts using ion implantation. The poly gate functions like masking tape in these steps. A second implant using boron ions forms the p -type sourcedrain for the p -channel transistors and p -type substrate contacts CSP. Instead these two masks function more like newspaper that prevents paint from spraying everywhere. The dopant ions are also blocked from reaching the silicon surface by the poly gates and this aligns the edge of the source and drain regions to the edges of the gates we call this a self-aligned process.

In addition, the implants are blocked by the FOX and this defines the outside edges of the source, drain, and substrate contact regions. We can do this by using a positive resist the pattern of resist remaining after developing is the same as the dark areas on the mask for one implant step and a negative resist vice versa for the other step. However, because of the poor resolution of negative resist and because of difficulties in generating the implant masks automatically from the drawn diffusions especially when opposite diffusion types are drawn close to each other or touching , it is now common to draw both implant masks as well as the two diffusion layers.

It is important to remember that, even though poly is above diffusion, the polysilicon is deposited first and acts like masking tape. It is rather like airbrushing a stripeyou use masking tape and spray everywhere without worrying about making straight lines.

The edges of the pattern will align to the edge of the tape.

Here the analogy ends because the poly is left in place. These names may refer to either the drawn diffusion layer that we call ndiff , the mask CSN , or the doped region on the silicon the intersection of the active and implant mask that we call n -diffusion very confusing. The source and drain are often formed from two separate implants.

The first is a light implant close to the edge of the gate, the second a heavier implant that forms the rest of the source or drain region. The separate diffusions reduce the electric field near the drain end of the channel. Tailoring the device characteristics in this fashion is known as drain engineering and a process including these steps is referred to as an LDD process , for lightly doped drain ; the first light implant is known as an LDD diffusion or LDD implant.

On top are the patterns as they appear in layout. Underneath are the magnified 8-by-8 pixel patterns. If we are trying to simplify layout we may use solid black or white for contact and vias. If we have contacts and vias placed on top of one another we may use stipple patterns or other means to help distinguish between them. Each stipple pattern is transparent, so that black shows through from underneath when layers are superimposed.

There are no standards for these patterns. When we draw layout you can see through the layersall the stipple patterns are ORed together.

This is how a p -channel transistor would look just after completing the source and drain implant steps. The insulating layers between the metal layers are not shown. Contact is made to the underlying silicon through a platinum barrier layer. Each via consists of a tungsten plug. Each metal layer consists of a titaniumtungsten and aluminum copper sandwich. Most deep submicron CMOS processes use metal structures similar to this. The scale, rounding, and irregularity of the features are realistic.

We can use diffusion for very short connections inside a logic cell, but not for interconnect between logic cells. Poly has the next highest resistance to diffusion. The stoichiometry of these deposited silicides varies. For example, for tungsten silicide W: There are two types of silicide process. In a silicide process only the gate is silicided. This reduces the poly sheet resistance, but not that of the sourcedrain. In a self-aligned silicide salicide process, both the gate and the sourcedrain regions are silicided.

In some processes silicide can be used to connect adjacent poly and diffusion we call this feature LI , white metal, local interconnect, metal0, or m0. The metal layer above the poly gate layer is the first-level metal m1 or metal1 , the next is the second-level metal m2 or metal2 , and so on. We can make connections from m1 to diffusion using diffusion contacts or to the poly using polysilicon contacts.

After we etch the contact holes a thin barrier metal typically platinum is deposited over the silicon and poly. Next we form contact plugs via plugs for connections between metal layers to reduce contact resistance and the likelihood of breaks in the contacts.

Tungsten is commonly used for these plugs. Following this we form the metal layers as sandwiches. The top and bottom layers are normally titaniumtungsten TiW, pronounced tie-tungsten. Submicron processes use chemicalmechanical polishing CMP to smooth the wafers flat before each metal deposition step to help with step coverage.

An insulating glass, often sputtered quartz SiO 2 , though other materials are also used, is deposited between metal layers to help create a smooth surface for the deposition of the metal. Design rules may refer to this insulator as an intermetal oxide IMO whether they are in fact oxides or not, or interlevel dielectric ILD.

We make the connections between m1 and m2 using metal vias , cuts , or just vias. We cannot connect m2 directly to diffusion or poly; instead we must make these connections through m1 using a via.

We call a process with m1 and m2 a two-level metal 2LM technology. A 3LM process includes a third-level metal layer m3 or metal3 , and some processes include more metal layers. The minimum spacing of interconnects, the metal pitch , may increase with successive metal layers. The minimum metal pitch is the minimum spacing between the centers of adjacent interconnects and is equal to the minimum metal width plus the minimum metal spacing.

Aluminum interconnect tends to break when carrying a high current density. Collisions between high-energy electrons and atoms move the metal atoms over a long period of time in a process known as electromigration. Copper is added to the aluminum to help reduce the problem.

The other solution is to reduce the current density by using wider than minimum-width metal lines. Tables 2. Notice that a m1 contact in either process is equal in resistance to several hundred squares of metal. If only one well layer is drawn, the other mask may be derived from the drawn layer. A single-well process requires only one well mask. The implant masks may be derived or drawn. Largely for historical reasons the contacts to poly and contacts to active have different layer names.

In the past this allowed a different sizing or process bias to be applied to each contact type when the mask was made. Arrows between objects denote a minimum spacing, and arrows showing the size of an object denote a minimum width. Rule 3.

Each of the rule numbers may have different values for different manufacturersthere are no standards for design rules. Dimensions are in l. Rule numbers are in parentheses missing rule sets are extensions to this basic process.

The rules in Table 2. If we use lambda-based rules we can move between successive process generations just by changing the value of l. For example, we can scale 0. You may get an inkling of the practical problems from the fact that the values for pad dimensions and spacing in Table 2.

This is because bonding to the pads is an operation that does not scale well. Often companies have two sets of design rules: Ideally we would like to express all of the design rules in integer multiples of l. In revision 7 rules 5. To ensure source and drain width. Different select types may touch but not overlap.

An index of '1' corresponds to a direct input to the second-stage cell. These rules are not standard, but form a convention that we shall adopt and one that is widely used in the ASIC industry. There are many ways to represent the logical operator, AND. I shall use an apostrophe like this, A', to denote the complement of A rather than A since sometimes it is difficult or inappropriate to use an overbar vinculum or diacritical mark macron. I shall be careful in these situations. Numbering is always in descending order.

We can express the function of the AOI cell in Figure 2. Sometimes we need to refer to particular inputs without listing them all. We can adopt another convention that letters of the input names change with the index position. There are 5 types and 14 separate members of each branch of this family. Here are the steps to construct any single-stage combinational CMOS logic cell: Draw a schematic icon with an inversion bubble on the last cell the bubble-out schematic. Form the n -channel stack working from the inputs on the bubble-out schematic: OR translates to a parallel connection, AND translates to a series connection.

If you have a bubble at an input, you need an inverter. Form the p -channel stack using the bubble-in schematic ignore the inversions at the inputsthe bubbles on the gate terminals of the p -channel transistors take care of these. If you do not have a bubble at the input gate terminals, you need an inverter these will be the same input gate terminals that had bubbles in the bubble-out schematic.

The two stacks are network duals they can be derived from each other by swapping series connections for parallel, and parallel for series connections.

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The n -channel stack implements the strong '0's of the function and the p -channel stack provides the strong '1's. The final step is to adjust the drive strength of the logic cell by sizing the transistors. Since the transistor lengths are normally equal to the minimum poly width for both types of transistors, the ratio of the transistor widths is also equal to 2. With the high dopant concentrations and high electric fields in submicron transistors the difference in mobilities is less typically between 1 and 1.

Logic cells in a library have a range of drive strengths. We normally call the minimum-size inverter a 1X inverter. An inverter with transistors that are twice the size will be an INVX2. Drive strengths are normally scaled in a geometric ratio, so we have 1X, 2X, 4X, and sometimes 8X or even higher, drive-strength cells.

We can size a logic cell using these basic rules: We can use the following method to calculate equivalent transistor sizes: We have to be careful to keep W and L reasonable. Since we cannot make a device 2 l wide and 1. We like to keep both W and L as integer multiples of 0.

The ratio in this library is thus 2. If we were to use four drive strengths for each of the AOI family of cells shown in Table 2. The synthesis tools can handle this number of cells, but we may not be able to design this many cells in a reasonable amount of time. Section 3. We connect a p -channel transistor to transmit a strong '1' in parallel with an n -channel transistor to transmit a strong '0'. We shall always define TG X, Y when we use it. Imagine we want to drive a '0' onto node Z from node A.

This is not what we want at all, the big capacitor has forced node A to a voltage close to a '0'. This type of problem is known as charge sharing. We should make sure that either 1 node A is strong enough to overcome the big capacitor, or 2 insulate node A from node Z by including a buffer an inverter, for example between node A and node Z. We must not use charge to drive another logic cell only a logic cell can drive a logic cell.

If we omit one of the transistors in a TG usually the p -channel transistor we have a pass transistor. There is a branch of full-custom VLSI design that uses pass-transistor logic. Much of this is based on relay-based logic, since a single transistor switch looks like a relay contact. There are many problems associated with pass-transistor logic related to charge sharing, reduced noise margins, and the difficulty of predicting delays. We can use two TGs to form a multiplexer or multiplexorpeople use both orthographies as shown in Figure 2.

We often shorten multiplexer to MUX. For example, is the select input X, Y, or Z? We must also be careful to label a MUX if we use the symbol shown in Figure 2. Thus, in Figure 2. Strictly this form of IEEE symbol should be used only for elements with more than one section controlled by common signals, but the symbol of Figure 2.

The MUX shown in Figure 2. We could buffer the output using an inverter Figure 2. To build a safe, noninverting MUX we can buffer the inputs and output Figure 2. The implementation in equation form 2. I often use an equation to describe a cell implementation. The following factors will determine which MUX implementation is best: Do we want to minimize the delay between the select input and the output or between the data inputs and the output?

Do we want an inverting or noninverting MUX? Some companies forbid such transmission-gate inputs since some simulation tools cannot handle them. Some companies will not allow this because of the dangers of charge sharing. What drive strength do we require and is size or speed more important? A minimum-size TG is a little slower than a minimum-size inverter, so there is not much difference between the implementations shown in Figure 2.

We are now using multiletter symbols, but there should be no doubt that A1' means anything other than NOT A1. This implementation only buffers one input and does not buffer the MUX output. We can use inverter buffers 3. The second approach has the following key advantages: These advantages of synchronous design especially the last one usually outweigh every other consideration in the choice of a clocking scheme. The vast majority of ASICs use a rigid synchronous design style.

The internal clock signals, CLKN N for negative and CLKP P for positive , are generated from the system clock, CLK, by two inverters I4 and I5 that are part of every latch cellit is usually too dangerous to have these signals supplied externally, even though it would save space. To emphasize the difference between a latch and flip-flop, sometimes people refer to the clock input of a latch as an enable. This makes sense when we look at Figure 2. When the clock input is high, the latch is transparent changes at the D input appear at the output Q quite different from a flip-flop as we shall see.

When the enable clock goes low Figure 2. The storage loop will hold its state as long as power is on; we call this a static latch.

A sequential logic cell is different from a combinational cell because it has this feature of storage or memory. Notice that the output Q is unbuffered and connected directly to the output of I2 and the input of I3 , which is a storage node. In an ASIC library we are conservative and add an inverter to buffer the output, isolate the sensitive storage node, and thus invert the sense of Q.

If we want both Q and QN we have to add two inverters to the circuit of Figure 2. This means that a latch requires seven inverters and two TGs 4.

The latch of Figure 2. A negative-enable active-low D latch can be built by inverting all the clock polarities in Figure 2. This flip-flop contains a total of nine inverters and four TGs, or 6. In this flip-flop design the storage node S is buffered and the clock-to-Q delay will be one inverter delay less than the clock-to-QN delay. Meanwhile the slave latch is disconnected from the master latch and is storing whatever the previous value of Q was. As the clock goes low the negative edge the slave latch is enabled and will update its state and the output Q to the value of node M at the negative edge of the clock.

The slave latch will then keep this value of M at the output Q, despite any changes at the D input while the clock is low Figure 2. When the clock goes high again, the slave latch will store the captured value of M and we are back where we started our explanation. The combination of the master and slave latches acts to capture or sample the D input at the negative clock edge, the active clock edge.

The behavior is shown on the IEEE symbol by using a triangular notch to denote an edge-sensitive input.

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A bubble shows the input is sensitive to the negative edge. To build a positive-edgetriggered flip-flop we invert the polarity of all the clocksas we did for a latch. The waveforms in Figure 2. We must keep the data stable a fixed logic '1' or '0' for a time t SU prior to the active clock edge, and stable for a time t H after the active clock edge during the decision window shown.

We say the trip point is 50 percent or 0. Common choices are 0. The flip-flop in Figure 2.

Some people use the term register to mean an array more than one of flip-flops or latches on a data bus, for example , but some people use register to mean a single flip-flop or a latch. This is confusing since flip-flops and latches are quite different in their behavior. When I am talking about logic cells, I use the term register to mean more than one flip-flop. To add an asynchronous set Q to '1' or asynchronous reset Q to '0' to the flip-flop of Figure 2.

For both set and reset we replace all four inverters: I2, I3, I6, and I7. An input that forces Q to '1' is sometimes also called preset. An input that forces Q to '0' is often also called clear. The arrows in Figure 2. We can break the connection between the inverter cells and use the circuit of Figure 2.

The symbol for the clocked inverter shown in Figure 2. We can use the clocked inverter to replace the inverterTG pairs in latches and flip-flops. For example, we can replace one or both of the inverters I1 and I3 together with the TGs that follow them in Figure 2. There is not much to choose between the different implementations in this case, except that layout may be easier for the clocked inverter versions since there is one less connection to make.

More interesting is the flip-flop design: We cannot replace inverter I6 because it is not directly connected to a TG. We can replace the TG attached to node M with a clocked inverter, and this will invert the sense of the output Q, which thus becomes QN.

If we wish to build a flip-flop with a fast clock-to-QN delay it may be better to build it using clocked inverters and use inverters with TGs for a flip-flop with a fast clock-to-Q delay. This should allow the user to better appreciate the potential of these innovating nanometer sized materials. Efforts of people in related fields are contained in this book. This book would be valuable to those who want to obtain knowledge and inspiration in the related area.

Author: Oleg Sergiyenko Publisher: InTech, This is the most complete book about optoelectromechanic systems and semiconductor optoelectronic devices.

The authors provide an accessible, well-organized overview of optoelectronic devices and properties that emphasizes basic principles. Author: Dragica Vasileska Publisher: InTech, The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book.

Author: Abbass A Hashim Publisher: InTech, Written for researchers who have chosen to study an area that appeals to them and one in which they show a genuine interest. It is targeted together to form the knowledge pathway to obtain an advanced polymeric research in polymer thin film. Author: Nicoleta Lupu Publisher: InTech, This book describes some nanowires fabrication and their applications, both as standing alone or complementing carbon nanotubes and polymers.

Understanding the design of nanowires described here, requires a multidisciplinary background.For example, for tungsten silicide W: This has a serious side. Common choices are 0.

This is very useful. The ASIC designer may not actually see the layout if it is hidden inside a phantom, but the layout will be needed eventually. We lose money on every partbut we make it up in volume.

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I do relish reading novels mostly . Also read my other articles. I have always been a very creative person and find it relaxing to indulge in mineral collecting.
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